Cadence Rapid System-Level Verification Techtorial
A Complete Holistic Verification Solution for System-on-Chip Designs
Overview
Achieving complete system verification and validation closure is among the most important challenges faced by designers and verification engineers. The ability to run multiple engines in multiple levels of abstraction and verify hardware and software in parallel increases system quality and helps teams meet schedules throughout the development process. The results include achieving first silicon working with first software.
This techtorial will cover the unique Cadence solution to this challenge through lectures, industry speakers, and case studies. It will also help you understand and leverage the latest products and flows that constitute the Cadence system-level verification methodology. This event is free and includes complimentary breakfast and lunch.
Highlights include:
Dates and Locations:
October 29th, 2008 (Wednesday)
Country Inn & Suites
5975 Lusk Blvd.
San Diego, CA, 92121
858.558.1818
October 30th, 2008 (Thursday)
Cadence Design Systems
16279 Laguna Canyon Road
Irvine, CA 92618
949.788.6080
November 11th, 2008 (Tuesday)
Lincolnshire Marriott Resort
Ten Marriott Drive
Lincolshire, IL 60069
847.634.1278
November 12th, 2008 (Wednesday)
Four Points by Sheraton Minneaplolis
1330 Industrial Blvd.
Minneapolis, MN 55413
612.331.1900
Agenda Overview: